1. Field of the Invention
This invention relates generally to the field of methods for DC parametric testing. More specifically, this invention relates to methods for minimizing ground bounce during DC parametric testing using boundary scan registers.
2. The Conventional Art
At least at one point during the manufacture of integrated circuits (ICs) it is desirable to test the integrity and performance of the interface between the IC and the outside world. This interface includes, among others, inputs, outputs, and power pins. Inputs and outputs can come in various types such as unidirectional, bidirectional, and 3-state. Power pins can have various DC voltage values such as ground, positive three, and positive five. The specific choices from among the various types of inputs, outputs, and power pins is dictated by the design of the IC.
One group of tests for integrity and performance of the IC interface are DC parametric tests. DC parametric tests consist of three sets of tests. First, there are the input parametric tests of voltage input low (VIL) and voltage input high (VIH). The purpose of the input parametric tests is to determine the DC characteristics of the IC interface with a logic 0 and a logic 1, respectively, driven at the inputs. Second, there are the output parametric tests of voltage output low (VOL) and voltage output high (VOH). The purpose of the output parametric tests is to determine the DC characteristics of the IC interface with the appropriate input to drive a logic 0 and a logic 1, respectively, at the outputs. Third, there is the leakage test for 3-state output buffers. The purpose of the leakage test is to determine the amount of current sunk or sourced by 3-state output buffers when they are in their high-impedance state.
Those of ordinary skill in the art will realize that a boundary scan register (BSR) is a multi-function register that usually resides between the input/output (I/O) buffers and the core logic of an IC. The BSR includes sets of storage cells, known as boundary scan (BS) cells. These BS cells can function in one of three ways. First, the BS cell can drive the input of an output buffer. Second, the BS cell can be driven by the output of an input buffer. Third, the BS cell can control the enable signal of one or more 3-state output buffer. A shift mode allows external control over the contents of the BS cells in the BSR. The shift mode in conjunction with a parallel drive mode allows control of the outputs independent of the core logic. Similarly, shift mode and parallel load mode provides observability of the inputs. Controlling the BSR is done using external I/O pins usually through a finite state machine.
Turning first to FIG. 1, a block diagram of IC 10 having a BSR is shown. Those of ordinary skill in the art will realize that the BSR shown is only for example purposes. The actual layout, order, function, and number of BS cells will depend on the specific application. Further, IC 10 may well have additional pins, depending on the design, which are not shown in the interest of clarity. In FIG. 1, the BSR starts with the BSR input pin 12. In accordance with the IEEE 1149.1 standard, the BSR input pin 12 is known as the test data in (TDI) pin. Next the BSR includes bidirectional output BS cell 16 (b0) connected between the core logic (not shown) of IC 10 and bidirectional output buffer 18 which is in turn connected to bidirectional pin 24. In this case, pin 24 is bidirectional so that it is also connected to bidirectional input buffer 30 which is in turn connected to bidirectional input BS cell 28 (b1) which is further in turn connected to the core logic. Bidirectional output enable BS cell 22 (e0) controls bidirectional output buffer 18. For reference purposes, also labeled are bidirectional output 20 and bidirectional input 26. Next the BSR includes 3-state output BS cell 34 (t0) which is connected between the core logic and 3-state output buffer 36 which is in turn connected to 3-state output pin 38. In this case, there is a second 3-state output BS cell 60 (t1) which is connected between the core logic and 3-state output buffer 62 which is in turn connected to 3-state output pin 64. 3-state output buffers 36 and 62 are controlled by 3-state output enable BS cell 56 (e1). Next the BSR includes 2-state output BS cell 42 which is connected between the core logic and 2-state output buffer 44 which is in turn connected to 2-state output pin 46. Next the BSR includes input BS cell 50 which is connected between the core logic and input buffer 52 which is in turn connected to input pin 54. Finally, the BSR ends with BSR output pin 68. In accordance with the IEEE 1149.1 standard, the BSR output pin 68 is known as the test data out (TDO) pin.
The remaining pins 14, 32, 40, 48, 58, and 66 are power pins which are connected to the power rails (not shown) of IC 10. During the discussion and examples that follow, whether a particular power pin (14, 32, 40, 48, 58, and 66) has a DC voltage value such as ground, positive three, or positive five will be stated if that distinction is required. Those of ordinary skill in the art will realize that IC 10 is unlikely to have as many power pins as are shown here. The large number of power pins shown here is in the interest of providing a flexible example, there is no requirement that IC 10 have this many power pins or that they exhibit the alternating pattern shown here to perform the present invention.
In general, the techniques involved in performing DC parametric tests are well known to those of ordinary skill in the art. The particular techniques used will depend on the design of the IC. A common set of techniques is described in the IEEE 1149.1 standard for JTAG BSRs.
Turning now to FIG. 2, a flow diagram of the steps of a conventional VIL test is shown. The conventional VIL test starts at step 80. Next, at step 82, all of the bidirectional outputs are disabled while all of the inputs are held at their initial value, whatever that initial value might be. Next, at step 84, a logic 0 is applied to all of the inputs simultaneously. Next, at step 86, the values that result from the application of logic 0 to all of the inputs is captured into the BSR. Next, at step 88, the contents of the BSR are shifted out while the BSR output pin is strobed for the expected values. Any value at the BSR output pin that is not as expected may indicate a problem and a failure of this test. The conventional VIL test ends at step 90.
Returning to FIG. 1, an example of the conventional VIL test shown in FIG. 2 will be illustrated. The conventional VIL test starts at step 80 of FIG. 2. Then, at step 82 of FIG. 2, bidirectional output buffer 18 is disabled by loading a disable value into bidirectional output enable BS cell 22 while the inputs at pins 26 and 54 are held at their initial value. Then, at step 84 of FIG. 2, a logic 0 is applied to input pins 26 and 54 simultaneously. Then, at step 86 of FIG. 2, the values that result from the application of logic 0 to input pins 26 and 54 is captured into the BS cells (28 and 50 respectively) of the BSR. Then, at step 88 of FIG. 2, the contents of the BS cells of the BSR are shifted out while the BSR output pin 68 is strobed for the expected value. The conventional VIL test ends at step 90 of FIG. 2.
Turning now to FIG. 3, a flow diagram of the steps of a conventional VIH test is shown. The conventional VIH test starts at step 92. Next, at step 94, all of the bidirectional outputs are disabled while all of the inputs are held at their initial value. Next, at step 96, a logic 1 is applied to all of the inputs simultaneously. Next, at step 98, the values that result from the application of logic 1 to all of the inputs is captured into the BSR. Next, at step 100, the contents of the BSR are shifted out while the BSR output pin is strobed for the expected values. The conventional VIH test ends at step 102.
An example of the conventional VIH test shown in FIG. 3 would be similar to the example illustrated for FIG. 2 above except that a logic 1 rather than a logic 0 is applied to input pins 26 and 54 at step 96 of FIG. 3.
Turning now to FIG. 4, a flow diagram of the steps of a conventional VOL test is shown. The conventional VOL test starts at step 104. Next, at step 106, all of the bidirectional input pins are floated externally. Next, at step 108, a logic 0 is loaded into all output BS cells and an output enabling value is loaded into all enable BS cells. Next, at step 110, the outputs are driven and the output pins are strobed for the expected value. The conventional VOL test ends at step 112.
Returning to FIG. 1, an example of the conventional VOL test shown in FIG. 4 will be illustrated. The conventional VOL test starts at step 104 of FIG. 4. Then, at step 106 of FIG. 4, bidirectional input pin 26 is externally floated. Then, at step 108 of FIG. 4, a logic 0 is loaded into output BS cells 16, 34, 42, and 60 and output enabling values are loaded into enable BS cells 22 and 56. Then, at step 110 of FIG. 4, the outputs are driven and pins 24, 38, 46 and 64 are strobed for the expected value. The conventional VOL test ends at step 112 of FIG. 4.
Turning now to FIG. 5, a flow diagram of the steps of a conventional VOH test is shown. The conventional VOH test starts at step 114. Next, at step 116, all of the bidirectional input pins are floated externally. Next, at step 118, a logic 1 is loaded into all output BS cells and an output enabling value is loaded into all enable BS cells. Next, at step 120, the outputs are driven and the output pins are strobed for the expected value. The conventional VOH test ends at step 122.
An example of the conventional VOH test shown in FIG. 5 would be similar to the example illustrated for FIG. 4 above except that a logic 1 rather than a logic 0 is loaded into output BS cells 16, 34, 42, and 60 at step 118 of FIG. 5.
Those of ordinary skill in the art will realize that when a conductor is switched from a logic 0 to a logic 1 or vice versa, the actual voltage on the conductor undergoes oscillations, called transients, before settling down to its final value. The amount of time, called the time constant, that it takes for these transients to settle down will depend on the amount of current involved in the switching and the values of the resistance, inductance, and capacitance (RLC) of the parasitic circuit formed by the conductor and its neighboring devices. The amplitude of these transients is directly related to the amount of current involved in the switching such that the greater the amount of current then the greater the amplitude.
In an IC, ground bounce, also called simultaneous switching noise and delta I noise, is the transient that occurs due to the presence of parasitic RLC circuits. With higher switching frequencies and smaller device dimensions, the parasitic RLC circuits can cause transients to appear on the power and ground rails. If the amplitude of these transients, either individually or in combination, is great enough, the IC may experience a malfunction and/or the DC parametric tests may be invalidated. Test invalidation may occur despite the fact that the IC under test could operate properly in its target environment because automatic test equipment (ATE) is generally more sensitive than the target environment for the IC. The magnitude of the ground bounce may depend on whether the conductor is being switched from logic 0 to logic 1 or vice versa. In either case, it is therefore important to control the generation of ground bounce when performing DC parametric tests.
Turning now to FIG. 6, a schematic of a CMOS inverter having modeled parasitic RLC circuits is shown. CMOS inverter 130 includes transistors 134 and 136 connected as shown between the core logic (not shown) of the IC and bonding pad 138. CMOS inverter 130 is shown further connected to power rail 140 (VDD) and ground rail 142. Those of ordinary skill in the art will realize that the CMOS inverter shown here is only one of many possible I/O buffers that are available and that the principles of ground bounce explained with respect to the CMOS inverter apply similarly to the other possible I/O buffers. CMOS inverter 130 is shown with model parasitic RLC circuit 144 connected between CMOS inverter 130 and power rail 140. Likewise, model parasitic RLC circuit 146 is connected between CMOS inverter 130 and bonding pad 138 and model parasitic RLC circuit 148 is connected between CMOS inverter 130 and ground rail 142.
Based on FIG. 6, ground bounce will occur when CMOS inverter 130 is switched from low to high or vice versa. For example, when CMOS inverter 130 is switched from low to high, the current drawn from power rail 140 causes parasitic RLC circuit 144 to oscillate. While the voltage value at power rail 140 remains constant, the voltage value at the point between parasitic RLC circuit 144 and CMOS inverter 130 goes through transients before settling down to essentially the same voltage value as that at power rail 140. It is ground bounce such as this that should be controlled when performing DC parametric tests.
One method of controlling the ground bounce generated during DC parametric tests is to employ IC design techniques that reduce the parasitic RLC circuits. These IC design techniques include increasing the width of the power and ground rails, having multiple power and ground rails, adding extra power and ground pins to evenly share the switching current, adding unequal delay paths to stagger switching times, and using output buffers with controlled or slow switching. Among the drawbacks to these IC design techniques are first that they are only available to one who is responsible for the IC design and are not available during testing of the IC and second that they are not always sufficient by themselves since the operations performed by a circuit during test may not be anticipated by the IC designers.
A second method of controlling the ground bounce generated during DC parametric tests is to perform the tests on a trial and error basis. That is, run one of the tests, if the test is invalid or causes damage to the IC then determine at which step in the test the problem occurred and redesign that step in the test. Through repetition of this process, eventually specific tests will be formulated. Among the drawbacks to this trial and error method is that time may be wasted running invalid tests and ICs may have to be sacrificed before specific tests are formulated. With the drive to higher integration densities and larger ICs, the cost associated with this method can be unacceptable.